View 21143-PD_155729.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w
w
w
.D
at
Sh a
et e
4U
.
om c
Upgrading to the 21143-PD and 21143-TD
Application Note
November 1998
w
w
w
.D
t a
S a
e h
t e
U 4
.c
m o
Order Number: 278232-001
w
w
w
.D
at
Sh a
et e
4U
.
om c
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 21143 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright (c) Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
Application Note
Upgrading to the 21143-PD and 21143-TD
Contents
1.0 Introduction......................................................................................................................... 1 1.1 1.2 2.0 3.0 4.0 5.0 6.0 7.0 Advantages of Upgrading to the 21143-xD ........................................................... 1 Physical Features of the 21143-PD and 21143-TD............................................... 1
Pinout Changes.................................................................................................................. 2 Package Marking Conventions...........................................................................................3 Cross-Referencing Package Markings............................................................................... 4 Upgrading Drivers ..............................................................................................................4 Register Differences Between 21143-xC and 21143-xD....................................................6 Miscellaneous Changes ...................................................................................................11 7.1 7.2 7.3 7.4 Wake-Up Frame Filter Register Block.................................................................11 JTAG Ring Boundary Shift Registers ..................................................................12 Wake-Up LAN Mode ...........................................................................................12 PCI/CardBus Signaling........................................................................................12
8.0 9.0
Comparing Programming Characteristics ........................................................................13 Hardware Characteristics .................................................................................................14
Figures
1 2 3 21143-TD Package Marking Conventions............................................................. 3 21143-PD Package Marking Conventions ............................................................ 4 Wake-up Frame Filter Register Block .................................................................11
Tables
1 2 3 4 5 6 Pin Changes and Descriptions (Sheet 1 of 2) ....................................................... 2 21143 Package Markings and Related Documentation ........................................ 4 Network and Communications Software Available for the 21143 ......................... 5 Register Differences Between 21143-xC and 21143-xD (Sheet 1 of 6)................ 6 Wake-up Frame Filter Register Block Field Assignments (Sheet 1 of 2) ............11 Programming Characteristics of the 21143-xC with the 21143-xD .....................13
Application Note
iii
Upgrading to the 21143-PD and 21143-TD
1.0
Introduction
The purpose of this document is to provide customers of the 21143 family with information to upgrade to its newest and most powerful members, the 21143-PD and the 21143-TD. This document describes how to upgrade your designs from the 21143-PC and 21143-TC, to the 21143-PD and 21143-TD. It also describes register-level differences, and serves as a convenient reference for upgrading customer-developed drivers. For detailed programming information and for register descriptions, consult the 21143 PCI/CardBus 10/100 Mb/s Ethernet LAN Controller Hardware Reference Manual (order number 278074).
1.1
Advantages of Upgrading to the 21143-xD
The 21143-PD and 21143-TD are pin compatible and are the functional equivalent of the 21143-PC and 21143-TC. However, they offer the following additional features and performance enhancements:
* Support network device class OnNow requirements for Microsoft's PC 97 and PC 98
specifications, including all wake-up events: -- Pattern matching -- Link change -- Magic Packet
* Fully compliant with Advanced Configuration and Power Interface (ACPI) Specification,
Revision 1.0.
* * * * * * *
Fully compliant with PCI Bus Power Management Interface specification, Revision 1.0. Support PCI/CardBus clock control through clkrun. Support CardBus cstschg pin and Status Changed registers. Support interrupt mitigation on transmit and receive. Improve power consumption in sleep and snooze modes. Support the electrical requirements of both PCI and CardBus pads. Support storage of CardBus Card Information Structure (CIS), also known as tuples, in the serial ROM or the external flash ROM. pin. The LED is On when a valid link is established, and Off when a valid link is not found.
* Provide a link indication for the 10BASE-T and the 100BASE-TX symbol interface on the same * Implement stretcher circuitry for the activity LED. This enables direct connection of the
21143-xD pin to the LED without the need for an external stretcher circuit.
* Provide link and activity indications on the same pin. * Implement signal-detection filtering to avoid false detection of a link in the 100BASE-TX
symbol interface.
* Provide three new PCI configuration registers. * Provide two new control status registers. * Implement fixes to erratas of the 21143-PC and 21143-TC.
1.2
Physical Features of the 21143-PD and 21143-TD
The 21143-PD and 21143-TD have the same body size and pin count as the 21143-PC and 21143-TC, making them drop-in replacements.
Application Note
1
Upgrading to the 21143-PD and 21143-TD
2.0
Pinout Changes
Table 1 lists the pins that have changed and includes the descriptions for the 21143-xC pins and the descriptions for the 21143-xD pins.
Table 1.
Pin Changes and Descriptions (Sheet 1 of 2)
21143-xC Pin Name 21143-xC Pin Description CardBus clock run indicates the clock status. The host system asserts clkrun_l to indicate normal operation of the clock. The host system deasserts clkrun_l when the clock is going to be slowed down to a nonoperational frequency. The 21143-xC samples clkrun_l, and when the signal is found deasserted, the 21143-xC asserts clkrun_l, requesting that normal clock operation be maintained. 21143-xD Pin Name Pin # Type 21143-xD Pin Description PCI/CardBus clock run indication. The host system asserts clkrun_l to indicate normal operation of the clock. The host system deasserts clkrun_l when the clock is going to be stopped or slowed down to a nonoperational frequency. If the clock is needed by the 21143, the 21143 asserts clkrun_l, requesting normal clock operation to be maintained or restored. Otherwise, the 21143 allows the system to stop the clock. Boot ROM address line bit 0. In a 256KB configuration, this pin also carries in two consecutive address cycles, boot ROM address bits 16 and 17. This pin also determines the types of signals to use for the PCI/CardBus output pins, either PCI or CardBus. By default, this pin selects PCI signaling. To select CardBus signaling, this pin must be connected to a pull-down resistor. This pin can be configured by software to be: * A general-purpose pin that performs either input or output functions. This pin can be configured by software to be: gep<2>/rcv_match * A general-purpose pin that performs either input or output functions. * A status pin that drives an LED to indicate a receive packet has passed address recognition. When the 21143 is in remote wake-up LAN mode, this pin is used as an indicator that a Magic Packet has been successfully detected. * A status pin that drives an LED to indicate a receive packet has passed address recognition. This pin can also be controlled by bit Func0_HwOptions<3> in the serial ROM to be a wake-up event pin that can be connected to pin pme# of the PCI connector or pin ctschg of the CardBus connector. When this pin is in a wake function, bit MiscHwOptions<1> in the serial ROM determines the polarity. The PME function takes precedence over the Magic Packet indication function. When the 21143 is in remote wake-up-LAN mode, this pin is used as an indicator that a Magic Packet has been successfully detected.
clkrun_l
86
I/O O/D
88
O
Boot ROM address line bit 0. In a 256KB configuration, this pin also carries in two consecutive address cycles, boot ROM address bits 16 and 17.
102
I/O
2
gep<2>/rcv_match/wake
br_a<0>/cb_pads_l
br_a<0>
clkrun_l
Application Note
Upgrading to the 21143-PD and 21143-TD
Table 1.
Pin Changes and Descriptions (Sheet 2 of 2)
21143-xC Pin Name 21143-xC Pin Description 21143-xD Pin Name Pin # Type 21143-xD Pin Description This pin can be configured by software to be: A general-purpose pin that performs either input or output functions. This pin can be configured by software to be: gep<3>10bt_link gep<3>/link * A general-purpose pin that performs either input or output functions. * A status pin that drives an LED to indicate that the 10BASE-T link integrity test has completed successfully after the link was down. A status pin that drives an LED to indicate: * Network link integrity state for 10BASE-T. * Network link integrity state for 100BASE-TX. * Both network activity and network link integrity state. * An input link status pin for OnNow support. When used with an MII PHY device, this pin should be connected to the MII PHY link indication pin (the 21143 interprets link-pass when this pin is high). This pin should not be left unconnected.
103
I/O
3.0
Figure 1.
Package Marking Conventions
The 21143-TD device uses the following conventions (Figure 1) for package markings. 21143-TD Package Marking Conventions
Pin 1 21143-TD Internal Control Number
DC1096x
External Order Number Site Code, Date Code, and Wafer Lot Number (varies)
i
Copyright information
S*YYWW*XXXXXX INTEL*(M)(C)*XXXX
The 21143-PD device uses the following conventions (Figure 2) for package markings.
Application Note
3
Upgrading to the 21143-PD and 21143-TD
Figure 2.
21143-PD Package Marking Conventions
Pin 1 21143-PD Internal Control Number
DC1096x
External Order Number Site Code, Date Code, and Wafer Lot Number (varies)
i
Copyright information
S*YYWW*XXXXXX INTEL*(M)(C)*XXXX
4.0
Cross-Referencing Package Markings
Use Table 2 to cross-reference the 21143 package markings with the related documentation.
Table 2.
21143 Package Markings and Related Documentation
External Order # 21143-PC 21143-TC 21143-PD 21143-TD
1.
Device 21143 21143 21143 21143
Device Type and Revision DC1071-C DC1071-C DC1096-B DC1096-B
Internal Part # 21-44085-12 21-44085-22 -- --
Package Type1 PQFP TQFP MQFP LQFP
Hardware Reference Manual # 278074 278074 278074 278074
Data Sheet # 278073 278073 278073 278073
For the 21143-xD, the PQFP package type has been reidentified as the MQFP, and the TQFP package type has been reidentified as the LQFP. This was done to conform to industry standard. The physical characteristics are the same for both package identifiers.
5.0
Upgrading Drivers
Software compatibility is retained for those customers utilizing Intel's drivers. This allows the same drivers and serial ROM format to be used with the 21143-PD and 21143-TD that were used for the 21143-PC and 21143-TC, providing the same functionality. For those customers who have developed their own drivers and require register-level information, see the section in this upgrade document titled, Register Differences Between 21143-xC and 21143-xD. Table 3 lists the network and communications software available for the 21143. For the latest driver and communications software information that takes advantage of the new features of the 21143-xD, see the components page available on the Intel World Wide Web Internet site at: http://developer.intel.com/design/network/new21/download/dsc-software-nc.htm
4
Application Note
Upgrading to the 21143-PD and 21143-TD
Table 3.
Network and Communications Software Available for the 21143
Drivers NDIS4 Unified DC21x4 driver Novell Server Unified DC21x4 driver Novell Client Unified DC21x4 driver NDIS2 Unified DC21x4 driver SCO UNIX Unified DC21x4 driver Support Files SROM Specification for DC21x4 devices SROM programming toolkit DVT Design Verification PCITEST diagnostic EVBDebug diagnostic CardBus Enabler BSDL NDISDBG Supports PC 97 compliant and supports Windows NT 4.0, Windows 95, and Windows 98 32-bit ODI drivers for Versions 3.1x and 4.x Novell servers; Client32 drivers for DOS 16-bit ODI drivers for DOS NDIS2 MAC drivers for DOS, OS/2, Windows 3.1, Windows for Workgroups 3.11, and Windows 95 SCO UNIX LLI, MDI, and MDI2 drivers
Description EEPROM data and format requirements for interoperability with DC21x4 drivers Serial ROM programming utilities Manufacturing test utility for verifying DC21x4 adapter functionality Utility to determine whether a PC is Revision 2.0 PCI compliant Utility for low-level debug and analysis of Intel 21x4 evaluation boards (or similar) Utility that maps CardBus slots into PCI configuration space for some CardBus laptops Boundary Scan Description Language files for Intel network chips Utility for low-level debug under Win 32 (Windows NT, Windows 95, and Windows 98) environment
Application Note
5
Upgrading to the 21143-PD and 21143-TD
6.0
Register Differences Between 21143-xC and 21143-xD
Enhancements to the 21143-xD have resulted in changes to existing registers and the addition of new registers.
Table 4.
Register Differences Between 21143-xC and 21143-xD (Sheet 1 of 6)
New or Different Items Configuration Registers New Capabilities. Indicates whether or not the 21143-xD implements a list of new capabilities: CFCS<20> Reserved * When set, this bit indicates the presence of New Capabilities. * When cleared, New Capabilities is not implemented. The value of this bit is loaded from Func0_HwOptions<3> bit (PME_Enable) in the serial ROM. CFRV<3:0> Step Number. Indicates the 21143-xC step number. The value of this field is set to 0. Revision Number. Indicates the 21143-xC revision number. The value of this field is set to 3. Address Space Indicator. This field indicates the location of the CIS base address. The 21143-xC supports only the value of 7 for this field, which means that the CIS begins in the expansion ROM space. Any other value causes the CIS register to reset to 0. Reserved Step Number. Indicates the 21143-xD step number. The value of this field is set to 1. Revision Number. Indicates the 21143-xD revision number. The value of this field is set to 4. Address Space Indicator. This field indicates the location of the CIS base address. The 21143-xD supports the value of 2, indicating that the CIS is stored in the serial ROM, and 7, indicating that the CIS is stored in the expansion ROM. Any value other than 2 or 7 may lead to unpredictable behavior. Capabilities Pointer Register. Offset 34h. Capabilities Pointer. Points to the location of the power-management register block in the PCI configuration space. CCAP<7:0> Reserved The value of this field is determined by Func0_HwOptions<3> bit (PME_Enable) in the serial ROM. If this bit is set, the value of this field is DCh; otherwise, this field is read as 00h. 21143-xC Registers 21143-xD Registers
CFRV<7:4>
CCIS<2:0>
CCAP
CWUC<0> CCID CCID<7:0>
Remote Wake-Up-LAN Disable. When set, disables the remote MBZ. This bit must not be written with a value of 1. wake-up-LAN mode. Not present Not present Capability ID Register. Offset DCh. Capabilities ID. PCI Power Management Registers ID. The value of this field is 01h, indicating that this is the power-management-register block. Next Item Pointer. Points to the location of the next block of the capability list in the PCI Configuration Space. The value of this field is 00h, indicating that this is the last item of the Capability linked list. Power Management PCI Version. The value of this field is 001Bh, indicating that the 21143-xD complies with Revision 1 of the PCI Power Management Specification.
CCID<15:8>
Not present
CCID<18:16>
Not present
6
Application Note
Upgrading to the 21143-PD and 21143-TD
Table 4.
Register Differences Between 21143-xC and 21143-xD (Sheet 2 of 6)
New or Different Items 21143-xC Registers 21143-xD Registers Power Management Event Clock. The value of this field is 0, indicating that the 21143-xD does not rely on the presence of the PCI/CardBus clock in order to generate a PME. Device Specific Initialization. The value of this field is 0, indicating that the 21143-xD does not require a special initialization code sequence in order to be configured correctly. D1 Support. The value of this field is 1, indicating that the 21143-xD supports the D1 power state. D2 Support. The value of this field is 1, indicating that the 21143-xD supports the D2 power state. PME Support D0. The value of this field is 0, indicating the 21143-xD does not assert PME in D0 power state. PME Support D1. The value of this field is 1, indicating that the 21143-xD may assert PME in D1 power state. PME Support D2. The value of this field is 1, indicating that the 21143-xD may assert PME in D2 power state. PME Support D3hot. The value of this field is 1, indicating the 21143-xD may assert PME in D3hot power state. PME Support D3cold. If this bit is set, the 21143-xD may assert PME in D3cold power state. Otherwise, the 21143-xD may not assert PME inD3cold. The value of this bit is loaded from Func0_HwOptions<6> bit in the serial ROM. Power Management Control and Status Register. Offset E0h. Power State. This field is used to set the current power state of the 21143-xD and to determine its power state. The definition of the field values are: 0 - D0 CPMC<1:0> Not present 1 - D1 2 - D2 3 - D3hot This field gets a value of 0 after power-up. PME_Enable. If this bit is set the 21143-xD can assert the gep<2>/rcv_match/wake pin. Otherwise, the assertion of the gep<2>/rcv_match/wake pin by the 21143-xD is disabled. This bit is cleared on power-up reset only, and is not modified by either hardware or software reset. PME_Status. This bit indicates that the 21143-xD has detected a power-management event. If the PME_Enable bit is set, the 21143-xD also asserts the gep<2>/rcv_match/wake pin. CPMC<15> Not present This bit is cleared on power-up reset or by write 1. It is not modified by either a hardware or software reset. When this bit is cleared the 21143-xD deasserts the gep<2>/rcv_match/wake pin. NOTE: This bit is also cleared if the General Enable bit of the FER (FER<4>) is cleared.
CCID<19>
Not present
CCID<21>
Not present
CCID<25> CCID<26> CCID<27> CCID<28> CCID<29> CCID<30>
Not present Not present Not present Not present Not present Not present
CCID<31>
Not present
CPMC
Not present
CPMC<8>
Not present
Application Note
7
Upgrading to the 21143-PD and 21143-TD
Table 4.
Register Differences Between 21143-xC and 21143-xD (Sheet 3 of 6)
New or Different Items 21143-xC Registers 21143-xD Registers
Control and Status Registers Enable OnNow Registers. When set, CSR1-PM and CSR2-PM are accessible. When this bit is cleared, writing to these registers is interpreted as writing to CSR1 and CSR2 (receive/transmit poll demand). This bit is cleared upon hardware or software reset. Wake-Up Frame Filter Register. This register is used for loading the wake-up frame filter register. In order to load the wake-up frame filter register, CSR0<26> must be set and CSR1-PM must be written eight times. Offset 80h. Value after reset is undefined. Wake-Up Frame Filter. The first value written to this register, after CSR0<26> was set, is loaded by the 21143-xD to the first longword in the wake-up frame filter register (filter_0_byte_mask). The second value written to this register is loaded to the second longword in the wake-up frame filter register block, and so on. NOTE: Complete details about the format of the wake-up frame filter register block are contained in the Miscellaneous Changes section of this document. Wake-Up Events Control and Status Register. This register is used for programming the requested wake-up events and the VLAN parameters. In order to program the requested wake-up events and the VLAN parameters, CSR0<26> must be set. Offset 10h. Value after reset is undefined. CSR2-PM<0> CSR2-PM<1> Not present Not present Link Change Enable. If set, enables generation of a power-management event due to link change. Magic Packet Enable. If set, enables generation of a power-management event due to Magic Packet reception. Wake-Up Frame Enable. If set, enables generation of a power-management event due to reception of a wake-up frame. Link Change Detected. If set, indicates that a power-management event was generated due to a link change. The bit is cleared by a write 1, or upon a power-up reset. It is unaffected by either a hardware or software reset. Magic Packet Received. If set, indicates that a power-management event was generated due to reception of a Magic Packet. The bit is cleared by a write 1, or upon a power-up reset. It is unaffected by either a hardware or software reset. Wake-Up Frame Received. If set, indicates that a power-management event was generated due to reception of a wake-up frame. The bit is cleared by a write 1, or upon a power-up reset. It is unaffected by either a hardware or software reset. MBZ. This bit must be zero. Global Unicast. When set, enables any unicast packet filtered by the 21143-xD address recognition to be a wake-up frame.
CSR0<26>
Reserved
CSR1-PM
Not present
CSR1-PM<31:0>
Not present
CSR2-PM
Not present
CSR2-PM<2>
Not present
CSR2-PM<4>
Not present
CSR2-PM<5>
Not present
CSR2-PM<6>
Not present
CSR2-PM<8> CSR2-PM<9>
Not present Not present
8
Application Note
Upgrading to the 21143-PD and 21143-TD
Table 4.
Register Differences Between 21143-xC and 21143-xD (Sheet 4 of 6)
New or Different Items CSR2-PM<11> 21143-xC Registers 21143-xD Registers VLAN Enable. When set, enable the 21143-xD's VLAN support. This field is reset upon hardware and software reset. VLAN Type. If the VLAN Enable bit is set (CSR2-PM<11>), this field should be written with the VLAN type defined by the IEEE 802.1 standard. Ignore Destination Address MSB. When set, bit 47 of the destination address is ignored in the MAC's address filtering. This bit is meaningful only if the 21143-xD is programmed to do perfect address filtering. It is cleared upon hardware and software reset. Number of Receive Packets. Indicates the number of receive packets before issuing a receive interrupt. Receive Timer. Indicates the time in units of "Cycle Size" before issuing a receive interrupt after packet reception. Number of Transmit Packets. Indicates the number of transmit packets before issuing a transmit interrupt. Transmit Timer. Indicates the time in units of "16*Cycle Size" before issuing a transmit interrupt after packet transmission. Cycle Size. This field controls the units for the transmit and receive timers. When set, the cycle size is: * 10BASE-T/AUI mode-12.8 s * MII/SYM 100 Mb/s mode-5.12 s CSR11<31> Reserved * MII 10 Mb/s mode-51.2 s When cleared, the cycle size is: * 10BASE-T/AUI mode-204.8 s * MII/SYM 100 Mb/s mode-81.92 s * MII 10 Mb/s mode-819.2 s Link Extend Enable. When set, the 21143-xD reports link detection on its 100BASE-TX symbol port only if its sd pin (pin 117) is asserted for at least 1.2 ms. When cleared, the 21143-xD reports link detection on its 100BASE-TX symbol port if its sd pin (pin 117) is asserted for at least 330 s. Function Event Register. This register is the CardBus Status Changed function event register, which is used for reporting of interrupt pending and power-management event detection in a CardBus system. Offset 80h. Value after reset is undefined for reserved bits; 0 for bits that are not reserved. General Wake-Up Event. This bit is set when the 21143-xD has detected a power-management event. This bit is cleared upon power-up reset and by write 1. It is unaffected by either a hardware or software reset. When the PME_Status bit in the PCI configuration is cleared, this bit is automatically cleared as well. FER<15> Not present Interrupt. This bit is set when there is an interrupt pending. This bit is cleared by write 1.
Not present
CSR2-PM<31:16> Not present
CSR6<26>
Reserved
CSR11<19:17> CSR11<23:20> CSR11<26:24> CSR11<30:27>
Reserved Reserved Reserved Reserved
CSR15<11>
Reserved
FER
Not present
FER<4>
Not present
Application Note
9
Upgrading to the 21143-PD and 21143-TD
Table 4.
Register Differences Between 21143-xC and 21143-xD (Sheet 5 of 6)
New or Different Items 21143-xC Registers 21143-xD Registers Function Event Mask Register. This register is the CardBus Status Changed function event mask register, which controls the assertion of the signals int_l and gep<2>/rcv_match/wake in a CardBus system. Offset 84h. Value after reset is undefined for reserved bits; 0 for bits that are not reserved. General Wake-Up Event Enable. When set together with the Wake-Up Event Summary Enable bit (FEMR<14>), enables the assertion of the gep<2>/rcv_match/wake pin. FEMR<4> Not present NOTE: To disable the assertion of thegep<2>/rcv_match/wake pin, the PME_Enable bit in the PCI configuration register (CPMC<8>) must be cleared as well. This bit is cleared upon power-up reset. Wake-Up Event Summary Enable. When set together with the General Wake-Up Event Enable bit (FEMR<4>), enables the assertion of the gep<2>/rcv_match/wake pin. FEMR<14> Not present NOTE: To disable the assertion of the gep<2>/rcv_match/wake pin, the PME_Enable bit in the PCI configuration register (CPMC<8>) must be cleared as well. This bit is cleared upon power-up reset. FEMR<15> Not present Interrupt Enable. When set, enables assertion of the interrupt pin (int_l). Function Present State Register. This register is the CardBus Status Changed function present state register, which is used for reporting the present state of the int_l and gep<2>/rcv_match/wake pins in a CardBus system. Offset 88h. Value after reset is undefined for reserved bits; 0 for bits that are not reserved. General Wake-Up Event. Reflects the current state of the wake-up event. This bit is cleared when either the General Wake-Up Event in the function event register is cleared, or when the PME_Status bit in the CPMC register is cleared. This bit is cleared upon power-up reset. Interrupt. This bit reflects the state of the interrupt line. It is set when the following conditions exist: FPSR<15> Not present CSR5<15> is set together with CSR7<15> or CSR5<16> is set together with CSR7<16>. The 21143-xD is in the D0 power state. FEMR<15> is set or Func0_HwOptions<7> (RealSTSCHG) bit in the serial ROM is cleared.
FEMR
Not present
FPSR
Not present
FPSR<4>
Not present
10
Application Note
Upgrading to the 21143-PD and 21143-TD
Table 4.
Register Differences Between 21143-xC and 21143-xD (Sheet 6 of 6)
New or Different Items 21143-xC Registers 21143-xD Registers Function Force Event Register. This register is the CardBus Status Changed function force event register, which is used to force the value of the interrupt and the general wake-up event bits in the function event register to a 1. Offset 8Ch. Value after reset is undefined for reserved bits; 0 for bits that are not reserved. Force Wake-Up. Writing 1 to this bit sets the wake-up event field in FER<4>, but not in FPSR<4>. If the wake-up event is enabled, the 21143-xD also asserts the gep<2>/rcv_match/wake pin. Writing 0 has no effect. This bit is cleared upon power-up reset. Force Interrupt. Writing 1 to this bit sets the Interrupt field in FER<15>, but not in FPSR<15>. If the interrupt is enabled, the 21143-xD also asserts the int_l pin. Writing 0 has no effect.
FFER
Not present
FFER<4>
Not present
FFER<15>
Not present
7.0
Miscellaneous Changes
The following are descriptions of additional changes incorporated into the 21143-xD.
7.1
Wake-Up Frame Filter Register Block
The wake-up frame filter register block is a new set of registers that is used by the 21143-xD to recognize wake-up frames. Figure 3 details the wake-up frame filter register block and Table 5 details the field assignments:
Figure 3.
Wake-up Frame Filter Register Block
Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask Filter 3 Byte Mask Reserved Filter 3 Command Reserved Filter 2 Command Reserved Filter 1 Command Reserved Filter 0 Command
Filter 3 Offset
Filter 2 Offset
Filter 1 Offset
Filter 0 Offset
Filter 1 CRC-16 Filter 3 CRC-16
Filter 0 CRC-16 Filter 2 CRC-16
Table 5.
Wake-up Frame Filter Register Block Field Assignments (Sheet 1 of 2)
Name Field MBZ This bit must be zero. Description
Filter 0-3 31 Byte Mask
Application Note
11
Upgrading to the 21143-PD and 21143-TD
Table 5.
Wake-up Frame Filter Register Block Field Assignments (Sheet 2 of 2)
Name Field Byte Mask 30:0 If bit number j of the byte mask is set, byte number pattern-offset + j of the incoming frame is processed by the CRC machine. Otherwise, byte pattern-offset + j is ignored. This field is not affected by either power-up, hardware, or software reset. Address Type Filter 0-3 3 Command Defines the destination address type of the pattern. When this bit is set, the pattern applies only to multicast frames. When this bit is cleared, the pattern applies only to unicast frames. Add Previous 2 When this bit is set, the 21143-xD performs a logical AND between the current filter matching signal and the matching signal of the previous filter. For the first filter, the 21143-xD chains the filter's matching signal with the result of the global unicast filter (CRS2-PM<9>). Inverse Mode 1 When this bit is set, the 21143-xD uses its match signal as a rejection signal. A frame that does not match this filter causes the 21143-xD to generate a power-management event. Enable Filter When this bit is set, filter i is enabled, otherwise, filter i is disabled. Pattern Offset Filter 0-3 Offset 7:0 The offset of the first byte in the frame that is examined by the 21143 in order to check if an incoming frame is a wake-up frame. Offset 0 is the first byte of the incoming frame's destination address. The minimum value allowed for this field is 12. This field is not affected by either power-up, hardware, or software reset. Pattern CRC16 Filter 0-3 CRC-16 15:0 This field contains the 16-bit CRC value calculated from the pattern and the byte mask programmed to the wake-up filter register block. The 21143-xD compares the result of its CRC machine to this value in order to determine whether the frame is a wake-up frame. This field is not affected by either power-up, hardware, or software reset. Description
0
7.2
JTAG Ring Boundary Shift Registers
The 21143-xD provides three new JTAG ring boundary shift registers: INTER3, BR_A0_OE, and
MII_MDC_OE.
7.3
Wake-Up LAN Mode
The 21143-xD wake-up-LAN mode operation has been modified so that it now asserts only the WAKE (gep<2>) pin when it detects a Magic Packet.
7.4
PCI/CardBus Signaling
The 21143xD PCI pads were modified to support CardBus signaling. The selection of PCI signaling or CardBus signaling is done through the br_a<0>/cb_pads_l pin. The 21143-xC supports only PCI signaling. To get CardBus signaling, external resistors are needed.
12
Application Note
Upgrading to the 21143-PD and 21143-TD
8.0
Comparing Programming Characteristics
Table 6 compares the programming characteristics of the 21143-xC with the 21143-xD.
Table 6.
Programming Characteristics of the 21143-xC with the 21143-xD
Characteristic Supports 1KB memory space Device revision VLAN enable Link LED for 100BASE-TX symbol interface Power-management register block Power-management register ID Power-management specification revision PCI clock present Auxiliary power source supplied Device-specific initialization Power state
1
21143-xC Unsupported CFRV<7:0>, 30h Unsupported Unsupported Unsupported Unsupported Unsupported Unsupported Unsupported Unsupported Unsupported CMBA<9:7>
21143-xD
CFRV<7:0>, 41h CSR2-PM<11><31:16> CSR15<11> CCAP<7:0> CCID<7:0> CCID<18:16> CCID<19> CCID<20> CCID<21> D1=CCID<25> D2=CCID<26> D0=CCID<27>, D1=CCID<28>, D2=CCID<29>, D3hot=CCID<30>, and D3cold=CCID<31> CPMC<1:0> CPMC<8> CPMC<15> CSR2-PM<4> CSR2-PM<6> FFER<4> FFER<15>
PME support Power state status (D0-D3) Power-management enable Power-management status Generate a power-management event after a wake-up frame Generate a power-management event after a Magic Packet Force a wake-up Force an interrupt event
1.
Unsupported Unsupported Unsupported Unsupported Unsupported Unsupported Unsupported Unsupported
This change can affect the behavior of software drivers.
Application Note
13
Upgrading to the 21143-PD and 21143-TD
9.0
Hardware Characteristics
The following table compares the temperature and power characteristics of the 21143-xC with the 21143-xD.
Characteristics Operating temperature range Package
1
21143-xC 0C to 70C (32F to 158F) 144-pin PQFP, 144-pin TQFP Vdd = 3.3 V, Vdd_clamp = 5 V or 3.3 V
21143-xD 0C to 70C (32F to 158F) 144-pin MQFP, 144-pin LQFP Vdd = 3.3 V, Vdd_clamp = 5 V or 3.3 V
Power supply Storage temperature range
1.
-55C to +125C (-67F to +257F) -55C to +125C (-67F to +257F)
For the 21143-xD, the PQFP package type has been reidentified as the MQFP, and the TQFP package type has been reidentified as the LQFP. This was done to conform to industry standard. The physical characteristics are the same for both package identifiers.
14
Application Note
Support, Products, and Documentation
If you need technical support, a Product Catalog, or help deciding which documentation best meets your needs, visit the Intel World Wide Web Internet site: http://www.intel.com Copies of documents that have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-332-2717 or by visiting Intel's website for developers at: http://developer.intel.com You can also contact the Intel Massachusetts Information Line or the Intel Massachusetts Customer Technology Center. Please use the following information lines for support:
For documentation and general information: Intel Massachusetts Information Line United States: Outside United States: Electronic mail address: 1-800-332-2717 1-303-675-2148 techdoc@intel.com
For technical support: Intel Massachusetts Customer Technology Center Phone (U.S. and international): Fax: Electronic mail address: 1-978-568-7474 1-978-568-6698 techsup@intel.com

▲Up To Search▲

Price & Availability of 21143-PD

	To Download 21143-PD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .